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CUTLASS SM120 Kernel Regression Halving MoE Throughput

NVIDIA's CUTLASS kernels for SM120 (and some Hopper architectures) suffer from a silent regression that halves throughput on Mixture of Experts (MoE) inference, commonly seen when utilizing certain PyTorch extensions or vLLM.

Quick answer

NVIDIA's CUTLASS kernels for SM120 (and some Hopper architectures) suffer from a silent regression that halves throughput on Mixture of Experts (MoE) inference, commonly seen when utilizing certain PyTorch extensions or vLLM.

Root cause
A bug in the CUTLASS epilogue generation for specific SM configurations causes sub-optimal register allocation and warp scheduling. Silent vendor regression introduced in recent CUDA toolkit updates impacting specialized grouped GEMMs used in MoE.
Recommended fix
Downgrade CUTLASS/CUDA toolkit to known-good version prior to the regression
How Denpex helps
Denpex investigates CUTLASS SM120 Kernel Regression Halving MoE Throughput using the evidence you provide or your connected workload collects. Earlier rank, host or application evidence is needed to distinguish an initiating failure from a downstream report.
Hardware/Vendor#cutlass#nvidia#moe#throughput#regression#vllm

What this failure is

CUTLASS SM120 Kernel Regression Halving MoE Throughput is a Hardware/Vendor failure seen during ML training runs. NVIDIA's CUTLASS kernels for SM120 (and some Hopper architectures) suffer from a silent regression that halves throughput on Mixture of Experts (MoE) inference, commonly seen when utilizing certain PyTorch extensions or vLLM. Common tags: Cutlass, Nvidia, Moe, Throughput.

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Why it happens (the mechanism)

A bug in the CUTLASS epilogue generation for specific SM configurations causes sub-optimal register allocation and warp scheduling. Silent vendor regression introduced in recent CUDA toolkit updates impacting specialized grouped GEMMs used in MoE. Taken together, these mechanisms explain why the failure is reproducible, why it tends to surface on specific workloads or scales, and why generic mitigation attempts often fall short without addressing the underlying cause.

What you'll observe

  • Throughput on MoE inference is roughly half of expected theoretical limits
  • No hard errors or exceptions are thrown during execution
  • GPU utilization appears artificially low (e.g., <50% utilization on $20K GPUs)

Common symptoms and what they mean

SymptomWhy it happens
vLLM or PyTorch throughput metrics show a 50% regression compared to previous baselineA bug in the CUTLASS epilogue generation for specific SM configurations causes sub-optimal register allocation and warp scheduling
NVIDIA Nsight Compute shows significant stall times in GEMM kernelsSilent vendor regression introduced in recent CUDA toolkit updates impacting specialized grouped GEMMs used in MoE
GPU SM active time is unusually low despite high request concurrencyA bug in the CUTLASS epilogue generation for specific SM configurations causes sub-optimal register allocation and warp scheduling

Which systems are affected

  • NVIDIA Hopper/Ada architectures (SM90/SM120)
  • MoE models (Mixtral, DeepSeek) running on vLLM or specialized PyTorch kernels

How to confirm this is the problem

Use this checklist to test the hypothesis against a small reproduction. No single line proves the root cause, so preserve the preceding events and compare one variable at a time.

  • ✓Reproduce the failure from a clean checkpoint/seed: the symptom must appear without warm-up state from a previous run.
  • ✓Verified signal present: vLLM or PyTorch throughput metrics show a 50% regression compared to previous baseline
  • ✓Verified signal present: NVIDIA Nsight Compute shows significant stall times in GEMM kernels
  • ✓Verified signal present: GPU SM active time is unusually low despite high request concurrency
  • ✓A targeted fix from the "How to fix it" section eliminates or substantially reduces the symptom within one validation pass.

Root cause

  • A bug in the CUTLASS epilogue generation for specific SM configurations causes sub-optimal register allocation and warp scheduling
  • Silent vendor regression introduced in recent CUDA toolkit updates impacting specialized grouped GEMMs used in MoE

The fix and how to prevent it

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vLLM errors in context

vLLM failures cross request, model, KV cache, worker, kernel and host boundaries. The hub compares common literal signatures and the first control that separates their causal owners.

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