GPU Uncorrectable ECC Memory Error (Xid 48/94/95)
GPU HBM memory experienced an uncorrectable ECC error (double-bit error) that the hardware cannot fix. This indicates physical HBM memory degradation requiring GPU drain and potential RMA.
GPU HBM memory experienced an uncorrectable ECC error (double-bit error) that the hardware cannot fix.
What this failure is
GPU Uncorrectable ECC Memory Error (Xid 48/94/95) is a GPU Memory failure seen during ML training runs. GPU HBM memory experienced an uncorrectable ECC error (double-bit error) that the hardware cannot fix. This indicates physical HBM memory degradation requiring GPU drain and potential RMA. Common tags: Gpu, Ecc, Memory, Hbm.
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Why it happens (the mechanism)
HBM3 memory cells wear out under sustained high temperature and voltage stress, transitioning from correctable (single-bit) to uncorrectable (double-bit) ECC errors. Manufacturing defects in HBM stack may cause early-life uncorrectable ECC failures. Temperature-induced voltage/frequency scaling amplifies timing margin violations in HBM I/O. Taken together, these mechanisms explain why the failure is reproducible, why it tends to surface on specific workloads or scales, and why generic mitigation attempts often fall short without addressing the underlying cause.
What you'll observe
- GPU memory controller detected a double-bit error that ECC cannot correct
- Xid 48, 94, or 95 logged to dmesg
- GPU may trigger row remap to map out defective memory cells
- Persistent uncorrectable ECC errors indicate physical HBM wear-out
Common symptoms and what they mean
| Symptom | Why it happens |
|---|---|
| dmesg shows Xid 48, 94, or 95 with ECC error context | HBM3 memory cells wear out under sustained high temperature and voltage stress, transitioning from correctable (single-bit) to uncorrectable (double-bit) ECC errors |
| nvidia-smi -q -d ECC shows non-zero Aggregate Uncorrectable errors | Manufacturing defects in HBM stack may cause early-life uncorrectable ECC failures |
| GPU memory bandwidth may degrade as bad rows are remapped | Temperature-induced voltage/frequency scaling amplifies timing margin violations in HBM I/O |
| NCCL timeouts or CUDA errors may follow as downstream effects | HBM3 memory cells wear out under sustained high temperature and voltage stress, transitioning from correctable (single-bit) to uncorrectable (double-bit) ECC errors |
Which systems are affected
- NVIDIA H100/H200/B100/B200 GPUs with HBM3/HBM3e memory
- GPUs under sustained high thermal load (near 700W power limit)
- Long-running training jobs (>7 days continuous)
- Multi-GPU nodes where one GPU failure drains the entire node
How to confirm this is the problem
Use this checklist to test the hypothesis against a small reproduction. No single line proves the root cause, so preserve the preceding events and compare one variable at a time.
- ✓Reproduce the failure from a clean checkpoint/seed: the symptom must appear without warm-up state from a previous run.
- ✓Verified signal present: dmesg shows Xid 48, 94, or 95 with ECC error context
- ✓Verified signal present: nvidia-smi -q -d ECC shows non-zero Aggregate Uncorrectable errors
- ✓Verified signal present: GPU memory bandwidth may degrade as bad rows are remapped
- ✓Verified signal present: NCCL timeouts or CUDA errors may follow as downstream effects
- ✓A targeted fix from the "How to fix it" section eliminates or substantially reduces the symptom within one validation pass.
The fix and the prevention pattern
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Xid 48 in context
Xid 48 is one of a small set of codes the NVIDIA driver uses to report GPU faults, and the number is most of the diagnosis: it tells you whether you are looking at your own code, the driver, or a board that needs replacing.
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Install the free VS Code extensionRoot cause
- HBM3 memory cells wear out under sustained high temperature and voltage stress, transitioning from correctable (single-bit) to uncorrectable (double-bit) ECC errors
- Manufacturing defects in HBM stack may cause early-life uncorrectable ECC failures
- Temperature-induced voltage/frequency scaling amplifies timing margin violations in HBM I/O
The fix and how to prevent it
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