Is this a hardware or a software issue?

Hardware failures can look like either layer depending on the symptom. The discriminator is the resolution of the symptom to the recommended fix: if applying the steps under "How to fix it" eliminates the symptom, this is a software/configuration class issue regardless of the hardware it surfaced on. Repeat the fix on a fresh node to confirm.

How long does the fix typically take?

Most resolutions from this entry take 10 to 30 minutes of engineer time once the diagnosis is confirmed. Long fixes come from skipping the diagnosis step and chasing apparent symptoms (validation drift, memory growth, slow throughput) instead of the actual root cause listed above. Apply the fix in a small experiment first, then roll it forward.

Does this affect inference or only training?

Primarily this is a hardware failure observed during training, but the same misconfiguration can leak into downstream evaluation and serving. Treat the prevention checklist as a guardrail: any pipeline that touches a trained checkpoint should re-validate the failure mode before promoting the model.

What's the cheapest way to confirm this is the problem?

Cheapest signal: reproduce the symptom on a 1-GPU toy run with the same configuration. If the toy run exhibits the same behavior, the cause is the configuration rather than the cluster. If only the multi-GPU run is affected, the failure is a distributed interaction, so PCIe Bus is the most likely layer to inspect.

Can the Denpex platform detect this automatically?

Yes. Denpex correlates the symptoms in this entry against your training logs in real time and surfaces the failure taxonomy, root cause, and exact remediation command on the console. Three full diagnoses are included free during signup, and the encyclopedia entry you are reading is generated from the same signal library that powers the platform.

What related failures should I check next?

Closely related failures cluster around #Xid Error. After applying this fix, validate against the related entries below to confirm no overlapping cause is masking as this one. Engineers routinely discover that the dominant failure mode is actually a second, sibling failure compounded on top.

Will this recur after the fix?

Applied once with the prevention checklist, this failure does not recur under normal operation. The recurring variant most engineers encounter is the re-emergence of the same symptom on a different model or stack after Xid Error is upgraded. Pin compatible versions and rerun the prevention smoke test on every dependency change.

Is there a fingerprint I can monitor?

Yes. Server periodically logs PCIe Advanced Error Reporting (AER) errors. is the highest-signal fingerprint. Wire a metric or alert on that signal (or its absence after the fix) so you can detect the recurrence automatically. The Denpex platform encodes this exact fingerprint and surfaces it directly in the dashboard.

What is the official documentation that covers this?

Reference documentation is listed in the References section at the bottom of this entry. The most authoritative URLs are the upstream framework docs and the issue trackers cited; the Denpex entry synthesizes both into the executive, engineer, and on-call perspectives so each audience can act without reading every linked source.

Does this entry include working code?

Yes. The "Code Examples" section contains copy-paste-ready snippets that target the most common stacks (PyTorch, Hugging Face Trainer, DeepSpeed, Megatron-LM, vLLM/Transformers). Each snippet is annotated with why it works so you can adapt the pattern to your own framework without losing fidelity.

Xid 43: PCIe Link Training Failure Under Load

Q: What does this failure look like in production?

In production this failure typically appears during the first tens-to-hundreds of training steps: loss curves become non-monotonic, validation metrics plateau above the baseline, and downstream checkpoints either diverge or fail to improve. Engineers frequently misread it as data drift when the underlying mechanism is poor physical seating of the gpu in the pcie slot, or a degraded pcie riser cable, degrades signal integrity. when the system shifts into high-bandwidth pcie gen4/gen5 states for inter-gpu communication, link training fails or bit errors overwhelm the error-correction. the resulting communication stall triggers the driver watchdog (xid 43).. Validating against the symptom list in this entry is the fastest way to confirm the diagnosis.

Q: How does this scale from 1 GPU to 1000 GPUs?

At single-GPU scale the symptom usually looks like slow convergence or a single anomalous loss value. At 64+ GPU scale, distributed interactions amplify poor physical seating of the gpu in the pcie slot, or a degraded pcie riser cable, degrades signal integrity. when the system shifts into high-bandwidth pcie gen4/gen5 states for inter-gpu communication, link training fails or bit errors overwhelm the error-correction. the resulting communication stall triggers the driver watchdog (xid 43). through collectives, and the failure can manifest as a full job abort. Always reproduce the fix at the smallest cluster configuration that still exhibits the symptom before promoting to production scale.

Poor physical seating of the GPU in the PCIe slot, or a degraded PCIe riser cable, degrades signal integrity. When the system shifts into high-bandwidth PCIe Gen4/Gen5 states for inter-GPU communication, link training fails or bit errors overwhelm the error-correction. The resulting communication stall triggers the driver watchdog (Xid 43).

Quick answer

Poor physical seating of the GPU in the PCIe slot, or a degraded PCIe riser cable, degrades signal integrity.

Symptom: During multi-GPU communication (e.g. NCCL AllReduce), the GPU driver halts with Xid 43.
Root cause: Poor physical seating of the GPU in the PCIe slot, or a degraded PCIe riser cable, degrades signal integrity. When the system shifts into high-bandwidth PCIe Gen4/Gen5 states for inter-GPU communication, link training fails or bit errors overwhelm the error-correction. The resulting communication stall triggers the driver watchdog (Xid 43).
Recommended fix: Reseat GPU and inspect PCIe slot N/A Physically removing and firmly reseating the GPU (and checking for dust/debris) often restores the signal integrity required for Gen4/Gen5 links.
How Denpex helps: Denpex matches Xid 43: PCIe Link Training Failure Under Load across every rank in a distributed run and reports which rank failed first, so you act on the initiating node instead of the loudest one.

Hardware#Xid Error

What this failure is

Xid 43: PCIe Link Training Failure Under Load is a Hardware failure seen during ML training runs. Poor physical seating of the GPU in the PCIe slot, or a degraded PCIe riser cable, degrades signal integrity. When the system shifts into high-bandwidth PCIe Gen4/Gen5 states for inter-GPU communication, link training fails or bit errors overwhelm the error-correction. The resulting communication stall triggers the driver watchdog (Xid 43). Common tags: Xid Error.

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Why it happens (the mechanism)

Often misdiagnosed as a software hang or a broken GPU, when the real culprit is a $20 PCIe riser cable or microscopic dust in the PCIe slot causing signal degradation.

What you'll observe

NVRM: Xid (PCI:0000:41:00): 43, Ch 00000000, engmask 00000101
pcieport 0000:00:03.0: AER: Corrected error received
pcie bus error: severity=Corrected, type=Physical Layer, id=0018

Common symptoms and what they mean

Symptom	Why it happens
Server periodically logs PCIe Advanced Error Reporting (AER) errors.	Poor physical seating of the GPU in the PCIe slot, or a degraded PCIe riser cable, degrades signal integrity. When the system shifts into high-bandwidth PCIe Gen4/Gen5 states for inter-GPU communication, link training fails or bit errors overwhelm the error-correction. The resulting communication stall triggers the driver watchdog (Xid 43).
During multi-GPU communication (e.g. NCCL AllReduce), the GPU driver halts with Xid 43.	Poor physical seating of the GPU in the PCIe slot, or a degraded PCIe riser cable, degrades signal integrity. When the system shifts into high-bandwidth PCIe Gen4/Gen5 states for inter-GPU communication, link training fails or bit errors overwhelm the error-correction. The resulting communication stall triggers the driver watchdog (Xid 43).
Sometimes the GPU completely disappears from the PCIe bus (Xid 79).	Poor physical seating of the GPU in the PCIe slot, or a degraded PCIe riser cable, degrades signal integrity. When the system shifts into high-bandwidth PCIe Gen4/Gen5 states for inter-GPU communication, link training fails or bit errors overwhelm the error-correction. The resulting communication stall triggers the driver watchdog (Xid 43).

Which systems are affected

PCIe Bus
Motherboard
NVIDIA GPU

How to confirm this is the problem

Use this checklist to test the hypothesis against a small reproduction. No single line proves the root cause, so preserve the preceding events and compare one variable at a time.

✓Check kernel logs for PCIe AER errors: dmesg | grep AER
✓Run DCGM diagnostics: dcgmi diag -r 1 to stress test the PCIe link.
✓Check PCIe link speed: nvidia-smi -q -d PCIE

Searchable error signature

search key

During multi-GPU communication (e.g. NCCL AllReduce), the GPU driver halts with Xid 43.
Sometimes the GPU completely disappears from the PCIe bus (Xid 79).

Use this text as a lookup key in logs and upstream issue trackers. It is not presented as a captured customer log. Confirm the cause from your own preceding events, versions, configuration and the cited references.

The fix and the prevention pattern

The root cause is on this page and stays free. A free account adds the exact remediation steps, saved history, and the fix on every entry in the encyclopedia.

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Xid 43 in context

Xid 43 is one of a small set of codes the NVIDIA driver uses to report GPU faults, and the number is most of the diagnosis: it tells you whether you are looking at your own code, the driver, or a board that needs replacing.

Compare every Xid code side by side

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Root cause

Poor physical seating of the GPU in the PCIe slot, or a degraded PCIe riser cable, degrades signal integrity. When the system shifts into high-bandwidth PCIe Gen4/Gen5 states for inter-GPU communication, link training fails or bit errors overwhelm the error-correction. The resulting communication stall triggers the driver watchdog (Xid 43).

The fix and how to prevent it

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References

↗NVIDIA Xid Errors: Resolving AER and Link Issues

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