Is this a hardware or a software issue?

Hardware failures can look like either layer depending on the symptom. The discriminator is the resolution of the symptom to the recommended fix: if applying the steps under "How to fix it" eliminates the symptom, this is a software/configuration class issue regardless of the hardware it surfaced on. Repeat the fix on a fresh node to confirm.

How long does the fix typically take?

Most resolutions from this entry take 10 to 30 minutes of engineer time once the diagnosis is confirmed. Long fixes come from skipping the diagnosis step and chasing apparent symptoms (validation drift, memory growth, slow throughput) instead of the actual root cause listed above. Apply the fix in a small experiment first, then roll it forward.

Does this affect inference or only training?

Primarily this is a hardware failure observed during training, but the same misconfiguration can leak into downstream evaluation and serving. Treat the prevention checklist as a guardrail: any pipeline that touches a trained checkpoint should re-validate the failure mode before promoting the model.

What's the cheapest way to confirm this is the problem?

Cheapest signal: reproduce the symptom on a 1-GPU toy run with the same configuration. If the toy run exhibits the same behavior, the cause is the configuration rather than the cluster. If only the multi-GPU run is affected, the failure is a distributed interaction, so NCCL is the most likely layer to inspect.

Can the Denpex platform detect this automatically?

Yes. Denpex correlates the symptoms in this entry against your training logs in real time and surfaces the failure taxonomy, root cause, and exact remediation command on the console. Three full diagnoses are included free during signup, and the encyclopedia entry you are reading is generated from the same signal library that powers the platform.

What related failures should I check next?

Closely related failures cluster around #Memory Access Violation. After applying this fix, validate against the related entries below to confirm no overlapping cause is masking as this one. Engineers routinely discover that the dominant failure mode is actually a second, sibling failure compounded on top.

Will this recur after the fix?

Applied once with the prevention checklist, this failure does not recur under normal operation. The recurring variant most engineers encounter is the re-emergence of the same symptom on a different model or stack after Memory Access Violation is upgraded. Pin compatible versions and rerun the prevention smoke test on every dependency change.

Is there a fingerprint I can monitor?

Yes. The training script crashes abruptly with a CUDA 700 error. is the highest-signal fingerprint. Wire a metric or alert on that signal (or its absence after the fix) so you can detect the recurrence automatically. The Denpex platform encodes this exact fingerprint and surfaces it directly in the dashboard.

What is the official documentation that covers this?

Reference documentation is listed in the References section at the bottom of this entry. The most authoritative URLs are the upstream framework docs and the issue trackers cited; the Denpex entry synthesizes both into the executive, engineer, and on-call perspectives so each audience can act without reading every linked source.

Does this entry include working code?

Yes. The "Code Examples" section contains copy-paste-ready snippets that target the most common stacks (PyTorch, Hugging Face Trainer, DeepSpeed, Megatron-LM, vLLM/Transformers). Each snippet is annotated with why it works so you can adapt the pattern to your own framework without losing fidelity.

NVLS Illegal Memory Access (CUDA Error 700)

Q: What does this failure look like in production?

In production this failure typically appears during the first tens-to-hundreds of training steps: loss curves become non-monotonic, validation metrics plateau above the baseline, and downstream checkpoints either diverge or fail to improve. Engineers frequently misread it as data drift when the underlying mechanism is nvls (nvlink sharp) offloads collective operations to the nvswitch hardware. an incompatibility between the nccl library version, the cuda toolkit, and the nvidia display driver can cause incorrect memory mappings to be passed to the nvswitch. when the switch attempts to read/write to the gpu memory space via these invalid addresses, it triggers a hard fault (illegal address).. Validating against the symptom list in this entry is the fastest way to confirm the diagnosis.

Q: How does this scale from 1 GPU to 1000 GPUs?

At single-GPU scale the symptom usually looks like slow convergence or a single anomalous loss value. At 64+ GPU scale, distributed interactions amplify nvls (nvlink sharp) offloads collective operations to the nvswitch hardware. an incompatibility between the nccl library version, the cuda toolkit, and the nvidia display driver can cause incorrect memory mappings to be passed to the nvswitch. when the switch attempts to read/write to the gpu memory space via these invalid addresses, it triggers a hard fault (illegal address). through collectives, and the failure can manifest as a full job abort. Always reproduce the fix at the smallest cluster configuration that still exhibits the symptom before promoting to production scale.

NVLS (NVLink SHARP) offloads collective operations to the NVSwitch hardware. An incompatibility between the NCCL library version, the CUDA toolkit, and the NVIDIA display driver can cause incorrect memory mappings to be passed to the NVSwitch. When the switch attempts to read/write to the GPU memory space via these invalid addresses, it triggers a hard fault (Illegal Address).

Quick answer

NVLS (NVLink SHARP) offloads collective operations to the NVSwitch hardware.

Symptom: NCCL WARN Cuda failure 700 'an illegal memory access was encountered'
Root cause: NVLS (NVLink SHARP) offloads collective operations to the NVSwitch hardware. An incompatibility between the NCCL library version, the CUDA toolkit, and the NVIDIA display driver can cause incorrect memory mappings to be passed to the NVSwitch. When the switch attempts to read/write to the GPU memory space via these invalid addresses, it triggers a hard fault (Illegal Address).
Recommended fix: NCCL_NVLS_ENABLE=0
How Denpex helps: Denpex investigates NVLS Illegal Memory Access (CUDA Error 700) using the evidence you provide or your connected workload collects. Earlier rank, host or application evidence is needed to distinguish an initiating failure from a downstream report.

Hardware#Memory Access Violation

What this failure is

NVLS Illegal Memory Access (CUDA Error 700) is a Hardware failure seen during ML training runs. NVLS (NVLink SHARP) offloads collective operations to the NVSwitch hardware. An incompatibility between the NCCL library version, the CUDA toolkit, and the NVIDIA display driver can cause incorrect memory mappings to be passed to the NVSwitch. When the switch attempts to read/write to the GPU memory space via these invalid addresses, it triggers a hard fault (Illegal Address). Common tags: Memory Access Violation.

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Why it happens (the mechanism)

A CUDA 700 error usually points to a bug in user-level PyTorch or CUDA code (e.g., an out-of-bounds array access). However, in this case, the user's code is perfectly fine; the memory violation is happening internally within NCCL's interaction with the NVLink switch fabric.

What you'll observe

NCCL WARN Cuda failure 700 'an illegal memory access was encountered'
cudaErrorIllegalAddress
NCCL WARN NVLS error

Common symptoms and what they mean

Symptom	Why it happens
The training script crashes abruptly with a CUDA 700 error.	NVLS (NVLink SHARP) offloads collective operations to the NVSwitch hardware. An incompatibility between the NCCL library version, the CUDA toolkit, and the NVIDIA display driver can cause incorrect memory mappings to be passed to the NVSwitch. When the switch attempts to read/write to the GPU memory space via these invalid addresses, it triggers a hard fault (Illegal Address).
Occurs specifically when initiating collective communications over NVLink via the SHARP/NVLS hardware offload.	NVLS (NVLink SHARP) offloads collective operations to the NVSwitch hardware. An incompatibility between the NCCL library version, the CUDA toolkit, and the NVIDIA display driver can cause incorrect memory mappings to be passed to the NVSwitch. When the switch attempts to read/write to the GPU memory space via these invalid addresses, it triggers a hard fault (Illegal Address).
The GPU state may become corrupted, requiring a system reboot to clear the CUDA context.	NVLS (NVLink SHARP) offloads collective operations to the NVSwitch hardware. An incompatibility between the NCCL library version, the CUDA toolkit, and the NVIDIA display driver can cause incorrect memory mappings to be passed to the NVSwitch. When the switch attempts to read/write to the GPU memory space via these invalid addresses, it triggers a hard fault (Illegal Address).

Which systems are affected

NCCL
CUDA
NVLink
NVIDIA B200
NVIDIA H100

How to confirm this is the problem

Use this checklist to test the hypothesis against a small reproduction. No single line proves the root cause, so preserve the preceding events and compare one variable at a time.

✓Run the script on a single GPU to see if the error disappears (confirming it's a multi-GPU/NCCL issue).
✓Disable NVLS via environment variable and observe if the crash stops.

Root cause

NVLS (NVLink SHARP) offloads collective operations to the NVSwitch hardware. An incompatibility between the NCCL library version, the CUDA toolkit, and the NVIDIA display driver can cause incorrect memory mappings to be passed to the NVSwitch. When the switch attempts to read/write to the GPU memory space via these invalid addresses, it triggers a hard fault (Illegal Address).

The fix and how to prevent it

Searchable error signature

search key

NCCL WARN Cuda failure 700 'an illegal memory access was encountered'
NCCL WARN NVLS error

Use this text as a lookup key in logs and upstream issue trackers. It is not presented as a captured customer log. Confirm the cause from your own preceding events, versions, configuration and the cited references.

The fix and the prevention pattern

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CUDA errors in context

CUDA reports errors asynchronously, so the traceback usually points at whatever line synchronised next rather than the one at fault. The hub covers every common CUDA error and how to make it report honestly.

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References

↗PyTorch Issue: CUDA failure 700 with NCCL

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