What does this failure look like in production?

In production this failure typically appears during the first tens-to-hundreds of training steps: loss curves become non-monotonic, validation metrics plateau above the baseline, and downstream checkpoints either diverge or fail to improve. Engineers frequently misread it as data drift when the underlying mechanism is a transient transmission failure on the nvlink or roce fabric propagates corrupted state to the sm. the gpu isolates the sm fault to prevent data corruption, emitting a containment xid without an actual memory bit flip.. Validating against the symptom list in this entry is the fastest way to confirm the diagnosis.

Is this a hardware or a software issue?

Hardware failures can look like either layer depending on the symptom. The discriminator is the resolution of the symptom to the recommended fix: if applying the steps under "How to fix it" eliminates the symptom, this is a software/configuration class issue regardless of the hardware it surfaced on. Repeat the fix on a fresh node to confirm.

How long does the fix typically take?

Most resolutions from this entry take 10 to 30 minutes of engineer time once the diagnosis is confirmed. Long fixes come from skipping the diagnosis step and chasing apparent symptoms (validation drift, memory growth, slow throughput) instead of the actual root cause listed above. Apply the fix in a small experiment first, then roll it forward.

Does this affect inference or only training?

Primarily this is a hardware failure observed during training, but the same misconfiguration can leak into downstream evaluation and serving. Treat the prevention checklist as a guardrail: any pipeline that touches a trained checkpoint should re-validate the failure mode before promoting the model.

What's the cheapest way to confirm this is the problem?

Cheapest signal: reproduce the symptom on a 1-GPU toy run with the same configuration. If the toy run exhibits the same behavior, the cause is the configuration rather than the cluster. If only the multi-GPU run is affected, the failure is a distributed interaction, so NCCL is the most likely layer to inspect.

Can the Denpex platform detect this automatically?

Yes. Denpex correlates the symptoms in this entry against your training logs in real time and surfaces the failure taxonomy, root cause, and exact remediation command on the console. Three full diagnoses are included free during signup, and the encyclopedia entry you are reading is generated from the same signal library that powers the platform.

What related failures should I check next?

Closely related failures cluster around #pcie/nvlink, #user-report. After applying this fix, validate against the related entries below to confirm no overlapping cause is masking as this one. Engineers routinely discover that the dominant failure mode is actually a second, sibling failure compounded on top.

Will this recur after the fix?

Applied once with the prevention checklist, this failure does not recur under normal operation. The recurring variant most engineers encounter is the re-emergence of the same symptom on a different model or stack after pcie/nvlink is upgraded. Pin compatible versions and rerun the prevention smoke test on every dependency change.

Is there a fingerprint I can monitor?

Yes. NVRM: Xid (PCI:0000:XX:00): 94, pid=XXXX, Contained: SM (0x1). RST: No, D-RST: No is the highest-signal fingerprint. Wire a metric or alert on that signal (or its absence after the fix) so you can detect the recurrence automatically. The Denpex platform encodes this exact fingerprint and surfaces it directly in the dashboard.

What is the official documentation that covers this?

Reference documentation is listed in the References section at the bottom of this entry. The most authoritative URLs are the upstream framework docs and the issue trackers cited; the Denpex entry synthesizes both into the executive, engineer, and on-call perspectives so each audience can act without reading every linked source.

Does this entry include working code?

Yes. The "Code Examples" section contains copy-paste-ready snippets that target the most common stacks (PyTorch, Hugging Face Trainer, DeepSpeed, Megatron-LM, vLLM/Transformers). Each snippet is annotated with why it works so you can adapt the pattern to your own framework without losing fidelity.

Fabric-Induced SM Containment Cascade

Q: How does this scale from 1 GPU to 1000 GPUs?

At single-GPU scale the symptom usually looks like slow convergence or a single anomalous loss value. At 64+ GPU scale, distributed interactions amplify a transient transmission failure on the nvlink or roce fabric propagates corrupted state to the sm. the gpu isolates the sm fault to prevent data corruption, emitting a containment xid without an actual memory bit flip. through collectives, and the failure can manifest as a full job abort. Always reproduce the fix at the smallest cluster configuration that still exhibits the symptom before promoting to production scale.

A transient transmission failure on the NVLink or RoCE fabric propagates corrupted state to the SM. The GPU isolates the SM fault to prevent data corruption, emitting a containment Xid without an actual memory bit flip.

Quick answer

A transient transmission failure on the NVLink or RoCE fabric propagates corrupted state to the SM.

Symptom: XID 137 (NVLink TLC RX PRIV Error)
Root cause: A transient transmission failure on the NVLink or RoCE fabric propagates corrupted state to the SM. The GPU isolates the SM fault to prevent data corruption, emitting a containment Xid without an actual memory bit flip.
Recommended fix: Restart the application pod and resume from checkpoint. - kubectl delete pod <faulty-pod>
How Denpex helps: Denpex investigates Fabric-Induced SM Containment Cascade using the evidence you provide or your connected workload collects. Earlier rank, host or application evidence is needed to distinguish an initiating failure from a downstream report.

Hardware#pcie/nvlink#user-report

What this failure is

Fabric-Induced SM Containment Cascade is a Hardware failure seen during ML training runs. A transient transmission failure on the NVLink or RoCE fabric propagates corrupted state to the SM. The GPU isolates the SM fault to prevent data corruption, emitting a containment Xid without an actual memory bit flip. Common tags: Pcie/Nvlink, User Report.

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Why it happens (the mechanism)

Xid 94 is documented exclusively as a 'Contained ECC Error'. Hardware operations teams will waste time trying to RMA a perfectly healthy GPU based on the assumption of failing memory.

What you'll observe

Multiple GPUs across different physical nodes simultaneously throw Xid 94.
The distributed training job hangs or crashes.
ECC error counters (DRAM/SRAM) remain strictly at zero.

Common symptoms and what they mean

Symptom	Why it happens
NVRM: Xid (PCI:0000:XX:00): 94, pid=XXXX, Contained: SM (0x1). RST: No, D-RST: No	A transient transmission failure on the NVLink or RoCE fabric propagates corrupted state to the SM. The GPU isolates the SM fault to prevent data corruption, emitting a containment Xid without an actual memory bit flip.
XID 137 (NVLink TLC RX PRIV Error)	A transient transmission failure on the NVLink or RoCE fabric propagates corrupted state to the SM. The GPU isolates the SM fault to prevent data corruption, emitting a containment Xid without an actual memory bit flip.
XID 74(NVLINK Error) detected	A transient transmission failure on the NVLink or RoCE fabric propagates corrupted state to the SM. The GPU isolates the SM fault to prevent data corruption, emitting a containment Xid without an actual memory bit flip.

Which systems are affected

NCCL
CUDA
NVLink

How to confirm this is the problem

Use this checklist to test the hypothesis against a small reproduction. No single line proves the root cause, so preserve the preceding events and compare one variable at a time.

✓Correlate Xid 94 timestamps across multiple nodes in the cluster using DCGM metrics.
✓Check `nvidia-smi -q -d ECC` to confirm counters have not incremented.
✓Look for preceding fabric errors like Xid 137 or Xid 74 in the dmesg logs.

Root cause

A transient transmission failure on the NVLink or RoCE fabric propagates corrupted state to the SM. The GPU isolates the SM fault to prevent data corruption, emitting a containment Xid without an actual memory bit flip.

The fix and how to prevent it

Searchable error signature

search key

XID 137 (NVLink TLC RX PRIV Error)
XID 74(NVLINK Error) detected
Multiple GPUs across different physical nodes simultaneously throw Xid 94.

Use this text as a lookup key in logs and upstream issue trackers. It is not presented as a captured customer log. Confirm the cause from your own preceding events, versions, configuration and the cited references.

The fix and the prevention pattern

The root cause is on this page and stays free. A free account adds the exact remediation steps, saved history, and the fix on every entry in the encyclopedia.

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Diagnose this failure in VS Code

Select the traceback or open the failed terminal, then run Denpex locally to see the initiating rank, collateral failures, exact fix, and verification command without uploading the log.

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References

Don't just read the fix, diagnose your run

The encyclopedia tells you what went wrong. Denpex tells you what went wrong in YOUR training run. With your logs, your config, and your stack.

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